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TMPeripheral
Imaging Corporation
PI616MC-AS 600DPI Image Sensor (CIS) PCB Engineering Data Sheet
DOCUMENT NUMBER REVISION NUMBER REV A
PAGES: 22 DATE: 12/20/02
PRODUCT SPECIFICATION
Reference: PI3039 Image Sensor Data Sheet
PAGE 1 OF 22 - PI616MC-AS, 12/20/02
1. DESCRIPTION
This data sheet covers the PI616MC-AS specification and brief description of the PI616MC-AS CIS Module. CIS stands for Contact Image Sensor. It is a one-dimension array of photosensitive elements, designed to image documents with a one-to-one magnification ratio. The sensors are sequentially cascaded to form a one dimensional variable-length line array in multiple integral numbers. Hence, providing the users desired lengths. The PI616MC-AS is one of these special length line-image arrays. It is configured with a total of 8 sub sections, each section containing a sequential line of 5 array sensors with its individual video output line. These 8 video outputs, are also referred to as tapped outputs. They are all readout in parallel. See Figure 1, Simplified Circuit Block Diagram. The 8 sub sections are all sequentially cascaded to form the one-dimensional array. It is fabricated on two PCB (Printed Circuit Board) referred to as sensor boards. Each sensor board contains 4 sub sections. The two sensor boards are cascaded in series to form a complete line image sensor of 8 sub sections with a total read length of @ 325mm. Accordingly, each sensor board contains 20 each of PI3039 image sensors, also a product of PIC. Hence, for both boards there are a total of 8 parallel tapped outputs and 40 each of the PI3039 image array sensors. Each chip has 192 photo sensing cells, hence, on one board there are 3840 cell sites and a total of 7680 cell sites for both board. Each cell site is a photo-detector that possesses its own independent processing circuit. An associated on-chip digital shift register scans and reads each photo detector's video signal on to a common output video line. In section of 5 sensors these common output video lines are individually brought out to the sensor boards' I/O connectors. There are two connectors, one on each board, each with four video outputs. These connectors are connected via a cable to their respective amplifier boards. See Figure 2, System Configuration Block Diagram. PI616MC-AS's schematic and its PCB mechanical outline drawing are attached to this data sheet.
2. OVERVIEW
The PI616MC-AS has 324.2 mm read width. Its recommended line rate is 192ms/line @ 5.0MHz clock rate, but its minimum can be low as 160ms/line @ it's maximum clocking speed of 6.0 MHz. Its sensor photo-site density is 23.25 elements/mm. See Peripheral Imaging Corporation's PI3039 data sheet that covers the specifications on the imaging array sensor. Operationally, it requires only the power supplies, +5V and -5V and two input clocks, one is the clock, CP, to operate the internal shift registers, second is the start pulse, SP, to initiate the output scan.
3. SCAN OUTLINE TABLE 3.1 SCANNING OUTLINE
ITEM READABLE WIDTH SENSOR PHOTO-SITE DENSITY NUMBER OF TOTAL ACTIVE SENSOR PHOTO-SITES SPECIFICATION 324.2 mm 23.25 elements/mm 7680 elements NOTE
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NUMBER OF PHOTO-SITE PER TAP TOTAL LINE READ TIME = READ TIME PER SECTION CLOCK FREQUENCY
960 192ms/line 160ms/line 5.0 MHz 6.0 MHz Typical, Tested @ 5.0 MHz Clock Minimum, Tested @ 6.0 MHz Clock Typical Maximum
4. PHYSICAL OUTLINE TABLE 4.1 PHYSICAL OUTLINE
ITEM IMAGE SENSORS SPECIFICATION PERIPHERAL IMAGING CORP. PI3039 PCB STIFFNER BOARD SIZE @355.6 mm X 41.3 mm X 6.35 mm SIZE 165.1mm X 21.4mm X 1.62mm 8 ANALOG VIDEO OUTPUTS TWO I/O CONNECTOR MOLEX 52610-1590 SIZE 291.3 mm X 76.2 mm X 1.6 mm TWO INPUTS: MOLEX 522071950 TWO OUTPUTS: ERNI-594083 NOTE SEE REFERENCED IMAGE SENSOR DATA SHEET
PCB STIFFNER BOARD SENSOR PCB DATA OUTPUT SENSOR BOARD CONNECTORS AMPLIFIER PCB BOARD AMPIFIER BOARD'S FOUR CONNECTORS
2 PCB MOUNTED ON THE STIFFENER USED TO CONNECT TO THEIR RESPECTIVE OUTPUT AMPLIFIERS MOUNTED ARE 8 OUTPUT AMPLIFIERS FOR EACH OF THE VIDEO LINES FROM THE SENSOR BOARDS
5. RECOMMENDED OPERATING CONDITIONS TABLE 5.1 RECOMMENDED OPERATING CONDITIONS (25 oC)
ITEM SYMBOL VDD IDD VSS MIN 4.5 135 TYPICAL 5.0 150 |-5.0| MAX 5.5 165 |-5.5| UNITS V ma V
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INPUT VOLTAGE AT DIGITAL LOW (INPUT CLOCKS SP AND CP) CLOCK FREQUENCY CLOCK PULSE HIGH DUTY CYCLE CLOCK HIGH DURATION INTEGRATION TIME
VIL FREQ (3) DUTY (4) TPW (3)(5) TINT
0 5.0 25 83.3 192ms/line 160ms/line 100
0.8 6.0 75
V MHz % ns, at 50%Duty Typical, Tested @ 5.0 MHz Clock Minimum, Tested @ 6.0 MHz Clock 0 C
OPERATING TEMPERATURE Notes:
TOP (6)
25
50
Note (1) Vpavg is a symbol representing the average value of every pixel in the complete line scan. Vp(n) is the pixel amplitude of nth pixel in a line scan. This measurement is taken with the image array under a uniform light exposure. The typical output is specified with a uniform input light exposure of 0.5mJ/cm2 from a blue Led light source. Note (2) Two saturated video output levels are specified. One is at the video signal's output amplifier, VSATA, and the other is at the input of the amplifier. In almost all applications, because the integration time is usually too short, there is not enough exposure time to saturate the array sensors. Accordingly, each output amplifier is fixed with a gain of @ 4.5. Note (3) FREQ is generally fixed for any application for the following reasons: One is the exposure time. With a given light power, the exposure time of the sensor depends on integration time, TINT, and in many of the applications it uses a clock count down circuits to generate the SP, shift register start pulse, hence, it will be related to the clock frequency. The second is the shape of the video output pulse. Because of the output video is in pulse charge packets, the signals are processed on the output video line of the sensors. Hence, the signal shape depends greatly upon the amplifier configurations. Please refer to the referenced PI3039 Data Sheet. It has some brief outline application notes. Under Note 6 in page 6 there is a discussion on video pulse shapes. On page 8, 9 and 10 there are discussions on the three types of signal output stages. Note (4) DUTY is the ratio of the clock's pulse width over its pulse period. Because the video pixel output resets during the clock pulse's high period and because the reset requires a finite resetting time, the clock duty cycle is recommended to operate within the following limits. See referenced data sheet in above note 3. Noting that the larger the DUTY, the less the signal amplitude, while too short of clock pulse will not provide enough video reset time and leaves residual charges, the recommended DUTY is 25% for frequencies < 5MHz and 50% for frequencies > 5MHz. Note (5) TINT is determined by time interval between two start pulses, SP. Hence, if SP is generated from a clock count down circuit, it will be directly proportional to clock frequency. And it will be synchronous with the clock frequency. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion and determine the desired tolerance level for the given system.
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Note (6) TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules and simple bench top tests using heat guns and freeze sprays. These will be re-measured during the pilot production under the standard QA practices that is under control of ISO 9000. 6.0 ELECTRO-OPTICAL CHARACTERISTICS
TABLE 6.1 ELECTRO-OPTICAL CHARACTERISTICS (25O C) PARAMETER SYMBOL PARAMETER NUMBER OF ACTIVE PHOTO DETECTORS PIXEL-TO-PIXEL SPACING LINE SCANNING RATE TINT
(1)
UNITS elements mm ms/line
NOTE
7680 43.25 192
CLOCK FREQUENCY
FREQ (2)
6.0
MHz
RED RESPONSIVITY GREEN RESPONSIVITY BLUE RESPONSIVITY BRIGHT OUTPUT VOLTAGE
ExpR (3) ExpG (3) ExpB (3) Vpavg (4)
70 55 35 3.0
V/mJ/cm2 V/mJ/cm2 V/mJ/cm2 Volts
@ 5.0 MHz clock frequency, see note 1. Maximum clock frequency, see note 2. See Note 3 for definition See Note 3 for definition See Note 3 for definition Green light, Exposure=X XXXXmJ/cm2
BRIGHT OUTPUT NONUNIFORMITY
ADJACENT PIXEL NONUNIFORMITY BRIGHT OUTPUT NONUNIFORMITY TOTAL DARK NONUNIFORMITY DARK VIDEO OFFSET RANDOM NOISE MODULATION TRANSFER FUNCTION
Up (5)
<7
%
Uadj (6) Uptotal (7)
<10 <10
% %
Depends on optical System. See note 5
Depends on the optical system, see note 5
Ud (8) Vd (9) RNL (10) MTF (11)
<25 -2.0 <11.8 <3.0 >70
mV Volts p-p mV rms mV %
Sensor only see note 11
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Notes: 1. TINT is the line-scan rate or integration time. It is determined by time interval between two start pulses, SP. Hence, if SP is generated from a clock count down circuit, it will be directly proportional to clock frequency. And it will be synchronous with the clock frequency. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-ofthumb. An experienced CIS user can use his discretion and determine the desired tolerance level for the given system. 2. FREQ is clock frequency, also equal to the signal data rate. It is generally fixed for many applications for following reasons: One is the exposure time. With a give light power, the exposure time of the sensor depends on integration time and in most applications it uses clock count down circuits to generate the SP, shift register start pulse. The second is the shape of the video output pulse. Because of the output is in pulse packets of video charges, the signal are processed on the output video line of the sensors. The signal shape depends greatly upon the amplifier configurations. Please refer to the referenced PI3039 Data Sheet. It has some brief outline application notes. Under Note 6 in page 6 there is a discussion on video pulse shapes. On page 8, 9 and 10 there are discussions on the three types of signal output stages. 3. The RESPONSIVITY is the ratio of video signal in volts divided by the unit exposure (Volts/micro-Joules/cm 2). This exposure was measured with the output level adjusted to 1.27V. The spread of the measured exposure R-RSP, G-RSP and B-RSP can be used to compute the user's desired signal voltage level. Since this is prototype module, all of the following notes 4, 5, 6, 7 and 8, are on data, based on engineering scope measurements, the data will be re-measured during pilot production using all the standard QA practices under the control of ISO 9000 regulations. Furthermore, they will be taken on fully computerized test systems. If required, these prototype data may be revised. 4. 5. Vpmax = maximum pixel value of Vp(n); Vpmin = minimum pixel value of Vp(n); Vpavg = a Vp(n)/7680; where Vp(n) is the nth pixel in a line scan with the module scanning a uniform white target. Vp values are measured with a uniform exposure. BRIGHT OUTPUT NONUNIFORMITY: Up(+) = [(Vpmax - Vpavg) / Vpavg] x 100% or Up(-)= [(Vpavg - Vpmin) / Vpavg] x 100%, whichever polarity with the highest value is selected. Two further notes, one is that the PI616MC-AS has no requirement for an optical system, or a light system. The second is that the non-uniformity is dominated by the LED light bar's non-uniformity so only the sensor non-uniformity is specified. The normal standard CIS modules are enclosed in a self-contained module with the complete optical and LED lighting system. So the light system, usually LED bar, is included in making the measurement of the optical characteristics. This fixes the optical geometry for the module and the light source. So the module's optical characteristics are simply measured with the module placed on a uniform reflecting target with a know reflection density. However, the PI616MC-AS is not enclosed with its optical and light source system. So Up is measured with uniform light source that directly illuminates the image sensors' photosite. ADJACENT PIXEL NONUNIFORMITY: Upadj = MAX[ | (Vp(n) - Vp(n+l) | / Vp(n)] x 100%. Upadj is non-uniformity in percentage of Vpavg. It is the maximum difference amplitude between two neighboring pixels. BRIGHT OUTPUT TOTAL NONUNIFORMITY: Uptotal = [Vpmax -Vpmin]/Vpavg DARK NONUNIFORMITY: Ud = Vdmax - Vdmin: It is measured over the full length of the array with the light source off and the sensors are placed in the dark. Vdmax is the maximum pixel value of the video pixel with the exposure off. Vdmin is the minimum
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6. 7. 8.
pixel value of the video pixel with exposure off. The references for these levels are the dark level, VDL. 9. DARK OUTPUT VOLTAGE, VDL is the level between the out video pixel dark level and the ground. 10. RANDOM NOISE, RNL, is measured using two methods, one is tangentially on the scope. This measures an approximate peak-to-peak, p-p, random thermal noise. The other is in terms of rms. It is estimated by using the Gaussian Statistical Methods. One pixel is selected out of a line scan and its peak values are recorded for a multiple line scans. These random peak values are used to estimate the rms values. 11. MODULATION TRANSFER FUNCTION depends on the optical system. Since this system relies on the users optical system it was not measured. Refer back to note 5, measurements on Up, all notes that references the optical measurements applies to MTF measurements as well. Using a conservative engineering estimate, the sensor's MTF is in excess of 70% at the Optical Nyquest Frequency.
7.0 ELECTRICAL CLOCKING CHARACTERISTICS. TABLE 7.1 CLOCK AMPLITUDE AND DUTY CHARACTERISTICS (Ta =25 OC) ITEM SYMBOL CONDITION SPECIFICATION MIN TYP MAX (1) CLOCK VIH For values See note INPUT see the notes (1) for VIL (1) VOLTAGE values CLOCK IIH (1) See note (1) INPUT (1) for IIL CURRENT values CLOCK FREQ (2) 0.100 5.0 6.0 FREQUENCY LINE READ TINT (3) 160 192 1000 TIME CLOCK RATIO= 25 50 75 PULSE DUTY tw/ to (4) CYCLE UNITS
MHz ms %
Note 1. These clock, CP, and start pulse, SP, values are compatible with CMOS 74HCXX series logic devices. Note 2. FREQ is not only the clock frequency, but is also equal to the pixel sample rate. See not 2 under Table 6.1. Note 3. TINT is the Line scan read time that depends on the interval between the start pulse entries. See note 1 under Table 6.1. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion and determine the desired tolerance level for the given system. Note 4. The definition for the symbols used in the RATIO is defined under the 7.2 Timing Diagram.
7.2 TIMING DIAGRAM
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TABLE 7.2 CLOCK TIMING CHARACTERISTICS, SEE FIGURE 3. TIMING DIAGRAM
This table is defines the symbols used in the timing diagram, Figure 3. Timing Diagram. It is for a single video section. However it applies to all eight video sections. Accordingly, the systemtiming diagram is a composition of this timing diagram repeated eight times with all waveforms in parallel, so electrically the system produces pixels from all eight video section simultaneously. ITEM SYMBOL MIN. TYPICAL MAX. UNITS CLOCK CYCLE TIME (2) CLOCK PULSE WIDTH (2) CLOCK DUTY CYCLE (2) PROHIBIT CROSSING TIME OF START PULSE DATA SETUP TIME DATA HOLD TIME SIGNAL DELAY TIME to tw duty tprh tds tdh tdl
(3)
0.1666 25 30 30 25
0.200 0.100 50
10 75
ms ns % ns ns ns ns
75
SIGNAL SAMPLE TIME tsmp 125 ns SIGNAL FALL TIME tsigf 75 ns RECOMMEND SP Tonoff (4) GENERATION 1. Applies to whole chart. All of the symbol definitions in above table are used in Figure 3, TIMING DIAGRAM. For the complete system, there are only two clocks, CP, and start pulse, SP and there logic levels are compatible with CMOS 74HCXX series logic devices. 2. See the notes on clock periods (the inverse of FREQ) and their duty cycle under Table 5.1 notes 3 and 4. 3. See PI3039 DATA SHEET page 6, Table 6A, note 6. 4. Recommend method for SP generation because the shift register loads only on the falling edge. 8.0 MAXIMUM RATINGS TABLE 8.1 MAXIMUM RATINGS (Not to be used for continuous operation) ITEM SYMBOL SPECIFICATION DC SUPPLY VOLTAGE VDD 7V INPUT VOLTAGE AMBIENT TEMPERATURE (1) VIN TA (PCB Surface) 0 TO VDD+0.3 0 TO 70OC (See note, below.) -10O to +75OC (See note, below.) 0 to 80% (See note) 70OC (See note, below.) NOTE SP & CP Operational Storage Non Condensing
AMBIENT HUMIDITY (1) MAXIMUM OPERATING CASE TEMPERATURE (1)
HA PCB Temperature
Note (1) All referenced parameters are conservative engineering estimate based on few of the prototype PCB. They are based on measurements of similar CIS modules and/or simple bench top tests using heat guns and freeze sprays. However these parameters will be re-measured during the pilot production using standard QA practices that is under the control of ISO 9000 regulations.
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9.0 I/O CONNECTOR PIN CONFIGURATION There are two I/0 connectors on the stiffener plate with the two sensor boards. They are MOLEX 52610-1590. They serve to interconnect the sensor boards to the amplifier boards. See the outline drawing of the system, Figure 2, System Configuration Block Diagram. Two 15 conductors strip lines serve as the interfacing harness. It is depicted with harnesses coming from under the stiffener plate and crossing to the top of the amplifier board and connecting to the two input connectors MOLEX 52207-1950. The final connectors are the two ERNI-594083. They are the SYSTEM I/Os. TABLE 9.1A SENSOR BOARD CONNECTORS AND INPUT CONNECTORS FOR AMPLIFIER BOARD PIN OUTS Only one of the two connectors on the stiffener board is specified because both connectors have identical pin out definitions. There are 8 video taps, 4 from each sensor board. They are sequential renumbered. The first sensor board video outputs are, 1, 2, 3 and 4. The second sensor board's videos are 5, 6, 7 and 8.
TWO MOLEX 52610-I590 AND ITS MATE TO AMPLIFIER BOARDS MOLEX 52207-1590 PIN PIN NAMES SYSMBOL I/0 NAMES AND FUNCTIONS NUMBERS 1 CLOCK PULSE CP I 2 3 4 5 6 7 8 9 10 11 12 13 START PULSE GROUND POWER SUPPLY GROUND GROUND GROUND VIDEO OUTPUT ANALOG GROUND VIDEO OUTPUT ANALOG GROUND VIDEO OUTPUT ANALOG GROUND SP GRD VDD GRD GRD GRD VSEC1 AGRD VSEC2 AGRD VSEC3 AGRD O I I I I I I I O I O I GROUND; 0V POSITIVE POWER SUPPLY GROUND; 0V GROUND; 0V GROUND; 0V TAPPED 1 VIDEO OUTPUT, SECTION 1 ON BOARD 1. IT IS SECTION 5 ON BOARD 2 ANALOG VIDEO RETURN LINE, GROUND; 0V TAPPED 2 VIDEO OUTPUT, SECTION 2 ON BOARD 1. IT IS SECTION 6 ON BOARD 2 ANALOG VIDEO RETURN LINE, GROUND; 0V
TAPPED 3 VIDEO OUTPUT, SECTION 3 ON BOARD 1. IT IS SECTION 7 ON BOARD 2 ANALOG VIDEO RETURN LINE,
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14 15
VIDEO OUTPUT ANALOG GROUND
VSEC4 AGRD
O I
GROUND; 0V TAPPED 4 VIDEO OUTPUT, SECTION 4 ON BOARD 1. IT IS SECTION 8 ON BOARD 2 ANALOG VIDEO RETURN LINE, GROUND; 0V
TABLE 9.1B AMPLIFIER BOARD OUTPUT CONNECTORS, ERNI-594083 There are four connectors on the amplifier board. Two are inputs, which are described above, and two are outputs, which are described below. There is only one table shown for both connectors. They are both identical in there connections except one is for sensor board 1's outputs and the other is for sensor board 2's outputs. Accordingly each of the video outputs, after amplification, for both sensor boards are labeled VOUT1, VOUT2, VOUT3 and VOUT4. Videos from sensor board 1, VSEC1's corresponding output is VOUT1, VSEC2's corresponding output is VOUT2, VSEC3's corresponding output is VOUT3 and VSEC4's corresponding output is VOUT4. Then the videos from sensor board 2 will have their corresponding outputs on the second connector VOUT1, VOUT2, VOUT3 and VOUT4, except they are outputs VOUT5, VOUT6. VOUT7 and VOUT8 because their video signals originate from section 5, section 6, section 7 and section 8 of the sensor board 2. ERNI CONNECTOR ERNI-594083 PIN NUMBERS DESCRIPTION ROW A 1 VDD 2 VDD 3 NO CONNECT 4 GROUND 5 SP 6 NO CONNECT 7 NO CONNECT 8 NO CONNECT 9 CLK 10 GND 11 NO CONNECT 12 NO CONNECT 13 NO CONNECT 14 GND 15 NO CONNECT 16 VSS DESCRIPTION ROW B VDD VDD NO CONNECT GROUND GND GND GND GND GND GND GND GND GND GND NO CONNECT VSS DESCRIPTION ROW C AGND VOUT1 AGND AGND AGND VOUT2 AGND AGND AGND VOUT3 AGND AGND AGND VOUT4 AGND AGND
Note: The functional description for the symbols used in the table below are same as described for the input connector. The two new symbols VSS and CLK are as follows: VSS is negative supply input. CLK is CP. The locations of pin 1 on all the connectors are facing the same end. See Figure 2, System Configuration Block Diagram.
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10.0 SCHEMATIC DIAGRAM Two reference schematic diagrams are attached. Only one schematic, CKT 1, Sensor Board Schematic, is required to represent both the sensor board 1 and 2 because the circuits are identical. The second one is for the amplifier board it contains all eight of the amplifiers on one schematic. The circuit description of its structure and operation has been briefly discussed in section 1, DISCRIPTION, page 2. Its operation follows from the discussion of the simplified block diagram. There are only two input control clocks for the circuits, the clock, CP, and the start pulse, SP. SP starts the shift register scanning while CP clocks the register and produces the video pixels at its same rate. The clocks are entered through the I/O connectors on both sensor boards. They are both externally buffered with the 74HC00 hexes and applied to inputs of the image sensors. On each of the two-image array sensor boards there are four sequential video sections. Each video section contains a row of 5 sequential image array sensors, PI3039. These are all clock in parallel with CP. The four sections on both boards are clocked with SP in parallel to initiate all eight video sections and simultaneously begin the eight sequential readouts. All eight lines, four in each sensor board, have reset switches, BU4S66, that parallel resets the video pixel charges after they are readout. These pixels, readout in parallel, are applied to their respective output amplifiers on the amplifier board. The second schematic, CKT 2, Amplifier Board Schematic, is the amplifier board. There are eight amplifiers for processing the output videos from both sensor boards. The amplifier board receives the inputs from sensor board output connector, J1, through two harnesses. They are connected into the input I/O connectors, J1 and J2, of the amplifier board. Since there are two sensor boards using the same schematic representation, the connector on sensor board 1, J1, becomes J2 for the second board. They are physically differentiated and marked as J1 and J2 on the Stiffener Board. Since all eight sections process their video signals through identical amplifiers, only one amplifier circuit is discussed. The AD8051 is an operational amplifier that is configured into non-inverting buffer amplifier with again of @ 4.5. It is used to isolate the video line from its external circuits. The isolated video line then serves as a storage capacitance for the pixels outputs. The pixel charges are read out onto the video line capacitance and integrated. This integrated pixel charges, converted to a voltage pulse, is amplified and produced at the output I/O. The reset switch on the video line, which is located on the sensor board schematic, resets the pixel signal charge prior to the readout of following pixel. 11.0 DRAWING ON MECHANICAL STRUCTURE Attached are 6 mechanical drawings. The first one, Top Assemble Outline, sheet 1of 1, shows an outline drawing of the complete CIS system, consisting of the Stiffener Plate, the interconnecting harness and the Amplifier Board. There are two connector Pin Configuration Tables, one for the two sensor boards and the input for the amplifier board. The other is for the two output connectors on the amplifier boards. These two tables show the pin numbering and names for the 6 connectors that are seen in the drawing. For detail descriptions of the interconnection and their functions, see section 9.0 CONNECTORS PIN CONFIGURATION, page 9. The second one, Stiffener Plate, is the view of the stiffener board. Stiffener board is 1/4" aluminum backing plate on which the two image sensor boards are mounted. It provides the dimensions of the plate, its access holes for the two-sensor board's connectors, along with all of the required dimensions. The third one, Two Sensor Board on the Stiffener, is a view of the two sensor boards mounted on the stiffener board. It shows the direction of the scan, its first pixel location and
PAGE 11 OF 22 - PI616MC-AS, 12/20/02
its video read line location. It provides the dimensions on the connector height, the thickness of PCB board and its component height. The fourth one, Connectors on Stiffener, is a backside view of the stiffener plate. It shows the location of the connectors and its pin order and direction. The fifth one, Amplifier Board, is a view of the PCB outline. The three views of the board provide the outline dimensions, its length, its width and its thickness. It also depicts the mounting holes and their dimensions and locations. The six one, Amplifier Board and Its Connectors, is view of the PCB with its connectors. 11.0 BLOCK DIAGRAMS; FIGURES 1, 2, AND 3
FIGURE 1. SIMPLIFIED CIRCUIT BLOCK DIAGRAM
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FIGURE 2, SYSTEM CONFIGURATION BLOCK DIAGRAM
FIGURE 3. TIMING DIAGRAM 12.0 SCHEMATIC DRAWINGS; CKT 1 AND CKT 2
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CKT 1. SENSOR BOARD SCHEMATIC
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CKT 2. AMPLIFIER BOARD SCHEMATIC
PAGE 15 OF 22 - PI616MC-AS, 12/20/02
Molex~52610-1590
Scan Direction Scan Direction
Molex~52610-1590 Molex~52207-1590 Pin signal assignments : Pin signal assignments : Pin Description Pin Description
Molex~52207-1590 ERNI~594083
ERNI~594083 Pin signal assignments : PIC version Pin
13.0 MECHANICAL DRAWINGS; DRW 1. 2. 3, 4, 5 AND 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK SP GND VDD GND GND GND VSEC1 Agnd VSEC2 Agnd VSEC3 Agnd VSEC4 Agnd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK SP GND VDD GND GND GND VSEC1 Agnd VSEC2 Agnd VSEC3 Agnd VSEC4 Agnd NOTE: 1. No component may excede 5.08mm (0.200inch) from ether side of the board. 2. The ERNI~594083 connectors are exempt from this height limit. 3. 3.175mm (0.125inch) clearance around 6 mounting holes. 4. Dimensions are in millimeter.
DRW 1. TOP ASSEMBLE OUTLINE
PAGE 16 OF 22 - PI616MC-AS, 12/20/02
Ingrid Chang Ingrid Chang 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Row A VDD VDD No connect GND SP No connect No connect No connect CLK GND No connect No connect No connect GND No connect VSS Description Row B VDD VDD No connect GND GND GND GND GND GND GND GND GND GND GND No connect VSS Description Row C Agnd Vout 1 Agnd Agnd Agnd Vout 2 Agnd Agnd Agnd Vout 3 Agnd Agnd Agnd Vout 4 Agnd Agnd 1
PI616MC-AS
A1
27-Nov-02
7
27-Nov-02
DRW 2. STIFFENER PLATE
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2
6
Scan Direction Sensor Board 1 Sensor Board 2
Scan Direction
See SIDE VIEW B. Reading Line Specification : (1) A1=5.000.2mm & A2=5.000.2mm. (2) | A1-A2 | = 0.4mm. (3) Both (1) & (2) use the stiffner plate edge as the reference. See SIDE VIEW A.
DRW 3. TWO SENSOR BOARD
Pin 1 Pin 15
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Top Layer (Sensor chip and components side) (Components Height) Bottom Layer (Connector side) (Connector Height)
3
6
Scan Direction
Scan Direction
Sensor Board 2 at the back side
Sensor Board 1 at the back side
Scan Direction
Scan Direction
(Pin 1 Location)
DRW 4. CONNECTORS ON STIFFENER
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(Pin 1 Location)
4
6
(PCB Thickness)
DRW 5. AMPLIFIER BOARD
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(PCB Thickness)
5
6
(ERNI~Connector Height)
(PCB Thickness)
DRW 6. AMPLIFIER BOARD WITH CONNECTORS
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(PCB Thickness)
6
6
(c)2002 Peripheral Imaging Corporation. Printed in USA. All rights reserved. Specifications are subject to change without notice. Contents may not be reproduced in whole or in part without the express prior written permission of Peripheral Imaging Corporation. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by Peripheral Imaging Corporation for its use nor for any infringement of patents or other rights granted by implication or otherwise under any patent or patent rights of Peripheral Imaging Corporation.
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